Arrangements for independent queuing/tracking of transaction portions to reduce latency

ABSTRACT

Arrangements directed to arrangements for queuing/tracking of transaction portions to reduce latency.

FIELD

[0001] The present invention is directed to arrangements forqueuing/tracking of transaction portions to reduce latency.

BACKGROUND

[0002] Often times within computing systems, and especially withinbridging devices, transactions such as read or write requests are passedbetween differing devices (e.g., interfaces) using queue arrangements.One arrangement is to let each device (e.g., interface) handle/processeach respective transaction independently from all other devices, and topass a transaction to a next sequential device once the device'shandling/processing of the transaction is complete. However, duringresearch leading to the present application, it was found that suchindependent/sequential passage and handling/processing of transactionsby sequential devices are disadvantageous in that a latency to move atransaction through the system is not minimized. Accordingly, what isneeded is a new and improved approach for the handling of transactionspassed from device-to-device within a system.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The foregoing and a better understanding of the present inventionwill become apparent from the following detailed description of exampleembodiments and the claims when read in connection with the accompanyingdrawings, all forming a part of the disclosure of this invention. Whilethe foregoing and-following written and illustrated disclosure focuseson disclosing example embodiments of the invention, it should be clearlyunderstood that the same is by way of illustration and example only andthe invention is not limited thereto. The spirit and scope of thepresent invention are limited only by the terms of the appended claims.

[0004] The following represents brief descriptions of the drawings,wherein:

[0005]FIG. 1 illustrates an example background interface queuearrangement useful in gaining a more thorough understanding/appreciationof the present invention;

[0006]FIG. 2 shown an example time chart of operations relating to theFIG. 1 example arrangement;

[0007]FIG. 3 illustrates an example advantageous interface queueembodiment in accordance with the present invention;

[0008]FIG. 4 shown an example time chart of operations relating to theFIG. 3 example arrangement;

[0009]FIG. 5 illustrates example contents of a request buffer of asending interface shown in FIG. 1;

[0010]FIG. 6 is a block diagram of an example system into whichembodiments of the present invention can be practiced; and

[0011]FIG. 7 is a block diagram showing example further details withrespect to a GXB block of FIG. 6.

DETAILED DESCRIPTION

[0012] Before beginning a detailed description of the subject invention,mention of the following is in order. When appropriate, like referencenumerals and characters may be used to designate-identical,corresponding or similar components in differing figure drawings.Further, in the detailed description to follow, examplesizes/models/values/ranges may be given, although the present inventionis not limited to the same. Still further, timing diagram FIGS. are notdrawn to scale, and instead, exemplary and critical time values arementioned when appropriate. Well known power/ground connections to ICsand other components may not be shown within the FIGS. for simplicity ofillustration and discussion, and so as not to obscure the invention.Further, arrangements may be shown in block diagram form in order toavoid obscuring the invention, and also in view of the fact thatspecifics with respect to implementation of such block diagramarrangements is highly dependent upon the platform within which thepresent invention is to be implemented, i.e., specifics should be wellwithin purview of one skilled in the art. Where specific details (e.g.,circuits, flowcharts) are set forth in order to describe exampleembodiments of the invention, it should be apparent to one skilled inthe art that the invention can be practiced without these specificdetails. Finally, it should be apparent that differing combinations ofhard-wired circuitry and software instructions can be used to implementembodiments of the present invention, i.e., the present invention is notlimited to any specific combination of hardware and software.

[0013] Turning now to more detailed description, FIG. 1 illustrates anexample disadvantageous interface queue arrangement useful in gaining amore thorough understanding of the invention. The disadvantageous FIG. 1example (as well as an transaction data and FL data into differing bitsof a same register entry (e.g., addressable memory location, byte).

[0014] The queue/pointer arrangement 120 further includes a comparator142, a transaction TrPushPointer 144, a transaction TrPopPointer 146, awrite pointer WrPtr, a read pointer RdPtr, with comparator 142generating a transaction TrValid signal (in an example manner describedahead).

[0015] Turning now to further description, FIG. 5 illustrates examplecontents of the request buffer 112 (of the sending interface 110) ingreater detail. More particularly, the request buffer 112 may includesufficient memory to store information with respect to a plurality oftransaction requests, e.g., sufficient buffer resources may be providedto accommodate a maximum expected number of transactions which may bewaiting/assembling at any given time within the sending interface 110.

[0016] A first example information of interest in discussion of the FIG.1 disadvantageous arrangement (as well as the FIG. 3 advantageousarrangement) is full line (FL) indication data. More particularly, it isknown in the art that it is more efficient to perform a memory access(e.g., of a main memory or a subsidiary buffer memory such as 190) byusing a full line (e.g., page) of memory rather than a plurality ofpartial line requests. Accordingly, the request buffer 112 includes anFL indication in correspondence with each of the transactions as anindication as to whether information sufficient to perform a full linememory access is available. More specifically, within the FL column ofFIG. 5, an “X” designation indicates a “don't care” situation, (i.e., an“X” or “don't care” designation may be irrelevant for certain types oftransactions, e.g., read transactions), a “Y” designation indicates afull line is ready for the corresponding transaction operation, andfinally, a dashed “--” designation indicates that a full line is not yetready for the corresponding transaction operation.

[0017] Further shown in the FIG. 5 request buffer 112 is a commandcolumn CMND including example transaction commands which, for examplepurposes, are labeled 1-LREAD, 2-HWRITE, 3-LWRITE, 4-FLUSH, 5-HWRITE and6-LWRITE, as well as an address ADDR column containing the correspondingaddresses AAA, BBB, CCC, DDD, EEE, and FFF, respectively.

[0018] In the disadvantageous FIG. 1/FIG. 5 arrangement, the sendinginterface 110 is arranged to buffer and assemble transactionsindependent of the queue/pointer arrangement 120 and receiving interface180, and to forward any transactions from the sending interface 110 onlyupon complete assembly of the transaction. More particularly, thesending interface maintains the buffered queue of transactions in orderto maintain an ordering of, and facilitate an assembly of, suchtransactions, and forwards any next transaction toward the receivinginterface only when all information with respect to the transaction iscompletely assembled.

[0019] In the FIG. 5 example, since the first transaction pertaining tothe 1-LREAD command having a “X” (don't care) FL designation and anaddress AAA, and likewise the second transaction pertaining to the2-HWRITE command with the “Y” (fully assembled) FL designation andaddress BBB, are both completely assembled, both such commands would beforwarded from the sending interface 110. In the FIG. 1/FIG. 5 examplegiven, the FL information is output along a WrLine forwarding path,whereas the CMND and ADDR information would be forwarded along a TxInfoforwarding path. In contrast, a third transaction relating to the3-LWRITE command having the “--” (not fully assembled) FL informationand the address CCC, would not yet be forwarded and would remainbuffered within the request buffer 112 of the sending interface 110,until all information with respect to such transaction is fullyassembled. Likewise, transactions subsequent to the not yet fullyassembled transaction would also not yet be forwarded so as to maintaina proper ordering of the transactions. The time chart 200 of FIG. 2shows the buffering/assembly and sending operations of the sendinginterface 110 as representative solid-lined blocks 210 and 220,respectively.

[0020] Once the FL information as well as the CMND and ADDR informationis forwarded to the integrated queue 130, stored, and such informationis treated in an integrated fashion within the integrated queue 130,e.g., the FL, CMND and ADDR information are all stored within a sameregister and are pointed to by a same pointer (WrPtr and/or RdPtr). Oncestored within the integrated queue 130, the TLB 136 arrangement is usedto translate the address portion ADDR of the transaction so as to relatean address of the transaction to an address of the main memory. NumerousTLB arrangements are known in the art and are not the main focus ofdiscussion of the present invention. Accordingly, the TLB arrangementoperation is only shown in representative form as dashed-block 136 inFIG. 1 and dashed-block 230 within the FIG. 2 time chart 200.

[0021] With forwarding of a transaction from the sending interface, thesending interface also performs a TrPush transaction to increment theTrPushPointer 144. Logic (not shown) may be adapted to be responsive tothe increment and completion of the TLB operation of the transaction,for example, to cause the WrPtr to change to point to, for example, thelatest transaction within the integrated queue 130 which has hadappropriate processing (e.g., translation) completed.

[0022] Periodically or at predetermined times, the comparator 142compares whether the RdPtr pointer is pointing to a same register as theWrPtr pointer, and if not (e.g., if the WrPtr pointer is “ahead” of theRdPtr pointer within the register files of the integrated queue), suchis an indication that there is an outstanding transaction waiting withinthe integrated queue to be performed and a predetermined TrValid signalis used to indicate such outstanding/ready status to the receivinginterface 180. Responsive to an indication of TrValid that there is anoutstanding/ready transaction waiting within the integrated queue 130,the receiving interface 180 performs a POP operation (shownrepresentatively by long-/short-dashed block 240 in FIG. 2) so as to POPa next sequential transaction (via the WrLine and TxInfo paths) from theintegrated queue 130, and uses a TrPop (FIG. 1) signal to increment theTrPopPointer 146 and thus the RdPtr pointer. The receiving interfacethen performs appropriate internal processing with respect to the POPPEDtransaction. Such internal processing is not a focus of this disclosure,and accordingly, detailed discussion thereof is omitted for sake ofbrevity.

[0023] A problem with the FIG. 1 disadvantageous arrangement is thattransactions are treated independently and sequentially by the differingFIG. 1 devices (e.g., interfaces) or components (e.g., queue/pointerarrangement). More particularly, the sending interface 110 buffers/holdsany respective transaction (and subsequent ordered transactions) untilsuch a time that the transaction information is substantially completed,and only then does it forward the completed transaction to the nextdevice or component integrated queue 130. This partially defeats thepurpose of the split transaction bus, as well as increases the size andcomplexity of the sending interface to support the required storage.

[0024] That is, the buffering/assembly is disadvantageous in a number ofregards. First, as indicated representatively by the FIG. 2 elongatedblock 210, such buffering/assembly represents a significant period oftime which adds to a latency of a transaction moving through the FIG. 1disadvantageous arrangement. That is, the CMND and ADDR information of aunassembled transaction within the request buffer 112 may becompleted/available well before the FL information completes, and sincethe buffered/delayed CMND and ADDR information is not yet forwarded tothe integrated queue 130, the TLB cannot begin its translationoperation. As a result, the TLB processing time is not “hidden” and addsto a latency of the transaction moving through the system. Second, thenecessity for sufficient request buffer resources within the sendinginterface 110 so as to store an expected number of unassembledtransactions at any given time represents an increase in design andoperational complexity and cost to the sending interface 110.

[0025] Accordingly, with the FIG. 1 disadvantageous arrangement, thetranslation operation is not initiated until a point in time sequentialto the sending of the assembled transaction request to the integratedqueue 130. Stated differently, the operations of the sending interface110 and the integrated queue 130 are performed sequentially in time,which represents an inefficient processing arrangement and adds again toa latency of the FIG. 1 disadvantageous arrangement. Further, the logicat the destination end of the queue gets no advance notice of incomingtransactions at and beyond a write until the associated data have beenreceived and that write is ready to be forwarded. This precludes hidingarbitration latency at the receiving end behind data latency at therequesting end, effectively making the pipeline across the queuecompletely serial in nature.

[0026] Discussion turns next to the advantageous example arrangement ofFIG. 3. Any components of FIG. 3 operating in a mannersimilarly/analogous to FIG. 1 components is labeled by a same referencenumeral and redundant discussion thereof is avoided for sake of brevity.Before detailed discussion of FIG. 3, mention of the following is inorder.

[0027] More particularly, the CMND/ADDR and FL information are executioninformation in that such information will be used to direct execution ofthe transaction, e.g., addressing, command-type or other types ofadministrative/management information for directing execution of thetransaction, rather than data (e.g., display pixel data) which is thesubject of the transaction note that data is directed through the DataBuffer RAM 190). That is, a transaction may contain both executioninformation useable to control execution of the transaction (i.e.,execution information) and transaction data (e.g., data to be storedwithin a memory). Accordingly, the CMND/ADDR information may beconsidered first execution information portions (e.g.,execution-direction bits of a transaction), and the FL information maybe considered second execution information portions (e.g., otherexecution-directing bits of a transaction). While the example embodimentof the present invention is, for the sake of brevity, described withonly two execution information portions, it should be understood that atransaction may have additional execution information portions or thatthe CMND/ADDR and FL information may be able to be subdivided into morethan two portions. Further, in situations where there are more than twoexecution information portions, practice of the present invention is notlimited to just two queue/pointer arrangements, i.e., practice may bemade with an increased plurality of queue/pointer arrangements, albeitat increased cost/complexity and timing/signal management of thearrangement.

[0028] Turning now to greater detail of the arrangement 300, the FIG. 3sending interface 310 operates somewhat differently from the FIG. 1sending interface 110. More particularly, rather thanbuffering/assembling complete transactions, the sending interface 310forwards sub-transaction information as it becomes completed, to theFIG. 3 queue/pointer arrangement 320. More particularly, as mentionedpreviously, the CMND and ADDR information of a transaction request maybe fully assembled well in advance of the FL information. The FIG. 3sending interface is adapted to take advantage of such fact byimmediately forwarding the CMND and ADDR information to thequeue/pointer arrangement 320, as illustrated representatively by theFIG. 4 solid-lined triangular block 420A within the time chart 400. As aresult thereof, the FIG. 3 combined read/write transaction queue 332 andthe TLB 336 arrangement/operation associated therewith can immediatelybegin to perform the TLB operation (as shown representatively by theshort-dashed block 430 in FIG. 4). Thus, the TLB operation may beperformed in parallel, while the sending interface continues todetermine the FL data with respect to the transaction. Accordingly, atime overhead of the TLB operation can be hidden by being performed inparallel with continued FL data determination, so as to further minimizea latency of transaction travel through the FIG. 3 example arrangement.

[0029] More particularly, as the TLB operation will take a knownpredetermined or average time for completion, the FL data completionoperation can be performed in parallel with the TLB translationoperation. Once the FL data is completed, the sending interface canforward such information to the full line queue 334 of the queue/pointerarrangement 320, as again shown representatively by the solid-linedtriangular block 420B in FIG. 4. Thus, in essence, the CMND and ADDRinformation is sent ahead, and subsequently, the FL data which is sentlater, catches up to the corresponding CMND and ADDR information withinthe queue/pointer arrangement 320. The CMND/ADDR and FL queues are“independent” in the sense that such queues can be loaded and/orunloaded with CMND/ADDR and FL information portions at completelydiffering times and with completely differing device-to-queue orqueue-to-device transmissions, i.e., loading/operations/unloading of thequeues are substantially, if not totally, independent from one another.

[0030] One advantage of the above-described operations of the exampleFIG. 3 arrangement is that the buffering resources within the sendinginterface 310 is substantially reduced and/or possibly even totallyeliminated in comparison with the FIG. 1 sending interface 110. Moreparticularly, since the CMND and ADDR information is immediatelyforwarded to the queue/pointer arrangement 320, and since such CMND andADDR information represents a good portion of any transaction, theamount of buffering resources to store the transaction is lessened oreliminated. That is, since the FL information will likewise beimmediately forwarded upon FL data completion, there may not be any needto even store the FL data within the sending interface 310. Further,even if it is necessary to store the FL data (e.g., for subsequenttransactions, to wait for bus access) within the sending interface 310,since such FL information is small in size, only a small amount ofbuffering capacity is needed within the sending interface 310.

[0031] In addition to the above-discussed advantage, the fact that thediffering CMND/ADDR and FL information portions are capable of beingindependently transmitted at differing times and/or within differingtransmissions from device-to-queue or queue-to-device, may lessentransmission path overhead required between the queues/devices. Forexample, since the CMND/ADDR and FL information portions are notrequired to be transmitted in parallel, perhaps a fewer number oftransmission paths could be provided between the queues/devices and beused in common to transmit the CNMD/ADDR and FL information portionsduring differing times.

[0032] As mentioned previously, the FL data is sent later to catch up tothe corresponding CMND and ADDR information within the queue/pointerarrangement 320. The advantageous reduction in latency and the reductionof sending interface buffer requirements is at a cost of increasedcomplexity of the queue/pointer arrangement 320. More particularly, itshould become apparent from the foregoing discussion that some type ofarrangement must be made to allow the CMND and ADDR information to besent ahead and the FL data to be sent later, and to have the FL datacorresponded or indexed to the appropriate CMND and ADDR information ofa same transaction. The FIG. 3 example arrangement accomplishes the samethrough use of independent queues and independent pointer arrangementsfor the independent queues.

[0033] More specifically, the FIG. 3 example arrangement is divided intotwo separate queue/pointer arrangements, i.e., a combined r/wtransaction queue 330 with corresponding pointer arrangement, as well asa full line queue 334 with its corresponding pointer arrangement. Whilethe FIG. 3 example arrangement is shown as essentially being dividedinto two independent queues and their corresponding pointerarrangements, practice of the present invention is not limited thereto,i.e., practice of the present invention can also be made with divisioninto additional queues and/or pointers. For example, the combined r/wtransaction queue arrangement 330 might be further divided into aindependent CMND queue and independent ADDR queue, with each againhaving an independent pointer arrangement. In addition, it should beunderstood that the independent queues may be provided in separatediscrete memories, as differing parts of a same memory, or anycombination thereof.

[0034] The combined r/w transaction queue 332 (similarly to theintegrated queue 130) operates in conjunction with a TLB 336 (which canbe provided in any combination of hardware and/or software), forperforming address translation for relating an address of a transactionto an address within the main memory. Again, the queue 330 operates withsome type of arrangement which maintains proper ordering of any queuedtransactions therein.

[0035] The combined r/w transaction queue arrangement 330 has associatedtherewith a pointer arrangement which includes a comparator 162, atransaction TxPushPointer 164, a transaction TxPopPointer 166, a writepointer WrPtr, a read pointer RdPtr, with the comparator 162 generatinga transaction queue TxValid signal (in an example manner describedahead). That is, again the combined r/w transaction queue arrangement330 (like the integrated queue 130) may be implemented as a registeredfile with rotating read and write pointers rather than a true FIFOstructure. Further, the pointer arrangements may be provided by anycombination of hardware and software.

[0036] With forwarding of the CMND and ADDR information from the sendinginterface 310, the sending interface also performs a transaction queueTxPush to increment the TxPushPointer 164. Logic (not shown) may beadapted to be responsive to the increment and completion of the TLBoperation with respect to the transaction, to cause the WrPtr pointer topoint to, for example, the latest transaction within the combined r/wqueue arrangement 330 which has had appropriate processing (e.g.,translation) completed.

[0037] Periodically or at predetermined times, the comparator 162compares whether the RdPtr pointer is pointing to a same queue 330register as the WrPtr pointer, and if not, (e.g., if the WrPtr pointeris “ahead” of the RdPtr pointer within register files of the queuearrangement 330), such is an indication that there is outstanding/readyCMND and ADDR data waiting within the queue and a predetermined TxValidsignal is used to indicate such outstanding/ready status to thereceiving interface 380. Responsive to an indication of TxValid thatthere is outstanding/ready CMND and ADDR waiting within the queue 330(as well as having an appropriate WrValid signal as described ahead),the receiving interface performs a POP operation (shown representativelyby long-/short-dashed block 440 in FIG. 4) so as to POP the nextsequential CMND and ADDR information (and FL information) from the queue330, and uses a TxPop (FIG. 3) signal to increment the TxPopPointer 166as well as the RdPtr pointer. Again, the receiving interface 380performs appropriate processing with respect to obtained information.Such internal processing is not a focus of this disclosures, andaccordingly, detailed discussion thereof is omitted for sake of brevity.

[0038] Similar discussions can be made with respect to the FL queue334's pointer arrangement which includes the comparator 152,WrPushPointer 154, WrPopPointer 156, write pointer WrPtr, read pointerRdPtr, with the comparator 152 instead generating a WrValid signalindicative of whether there is outstanding FL data waiting within thequeue 334. Again, responsive to the WrValid signal that there isoutstanding/ready FL data waiting, the receiving interface 380 performsa POP operation when appropriate to obtain the next sequential FL dataas well as to output a WrPop signal to increment the WrPopPointer 156.

[0039] With respect to maintaining a correspondence between theCMND/ADDR information and the FL information, as long as CMND/ADDRinformation and FL information is pushed into the queues 330 and 334,respectively, in one-to-one correspondence, as long as an ordering ofsuch information within the independent queues is maintained, then suchcorrespondence between the CMND/ADDR and FL information should bemaintained and appropriately related CMND/ADDR and FL information shouldbe able to be POPPED from the queues 330 and 334 in correctcorrespondence. Practice of the present invention is not limited to sucharrangement, as many differing approaches could be used to maintaincorrespondence between the CMND/ADDR and FL information within thequeues, e.g., an indexing table.

[0040] More particularly, the term “pointer” is used/meant in a genericsense within the present disclosure, in that there are numerous possibleways to accomplish a pointer arrangement. While the above exampleembodiment used a pointer arrangement to independently keep track ofun-popped ones of the CMND/ADDR and FL information portions within theindependent queues, an alternative pointer arrangement could be used forkeeping correct correspondence between appropriate ones of the CMND/ADDRand FL information portions. For example, matching sequence numberscould be assigned/stored with respect to both the CMND/ADDR and FLinformation portions for any given transaction, i.e., within theindependent queues. A “ready” bit be used/stored with respect to eachone of the CMND/ADDR information portions to flag which portions havehad TLB processing completed. The matching sequence numbers could thenbe used to effect simultaneous unloading of corresponding ones of theCMND/ADDR and FL information portions from the queue, or to later matchup corresponding ones of the CMND/ADDR and FL information portions(e.g., within the receiving interface). Further, it should be understoodthat practice of the present invention is not limited to the queueshaving matching or similar pointer arrangements, i.e., practice may alsobe made by the queues having completely differing pointer arrangementsfrom one another.

[0041] Turning discussion next to the receiving interface 380, suchreceiving interface 380 operates somewhat differently from the FIG. 1receiving interface 180. More particularly, since the FIG. 1CMND/ADDR/FL information is maintained within an integrated queue 130having only a single pointer arrangement associated therewith, the FIG.1 receiving interface 180 is responsive only to the singular TrValidsignal in determination of whether it is appropriate to POP CMND/ADDR/FLinformation from the queue 130 and to increment a TrPopPointer. Incontrast, the FIG. 3 example arrangement having independently operatingqueues 330, each having its own independent pointer arrangement, mustlook at a number of valid signals to determine whether CMND/ADDR and FLinformation are appropriate to be POPed from the queues 330 and 334 anda plurality of POP pointers are incremented upon a POPing action. Morespecifically, the receiving interface 380 monitors both the TxValid andWrValid signals for appropriate indication that both CMND/ADDR and FLinformation are ready/waiting within the queues 330 and 334,respectively. Only upon both valids does the receiving interface 380 POPsuch information, and then increment both the TxPopPointer 166 and theWrPopPointer 156.

[0042] Accordingly, although practice of the present invention may bemade by POPPING the CMND/ADDR and FL information for any giventransaction simultaneously, practice might be alternatively made byPOPPING such information at different times. The approach of POPPING theinformation at different times might be advantageous in allowing thereceiving interface to immediately start processing of sub-portions of atransactions, rather than writing to POP complete transactioninformation. If POPPING of CMND/ADDR and FL information are conducted atdiffering times by the receiving interface 380, then the interface 380has the responsibility (e.g., via indexing) of maintainingcorrespondence between such information.

[0043] A time-savings benefit of the FIG. 3 advantageous arrangementover the FIG. 1 arrangement can be seen by a comparison of the timecharts 400 and 200 of FIGS. 4 and 2, respectively. More particularly,referencing FIG. 4, since the FIG. 3 advantageous arrangement no longerrequires completion of the FIG. 2 buffer/assemble operation 210 beforesending, and further, since the translation operation 430 can beconducted by the TLB 336 substantially or majorly overlappingly (i.e.,in parallel) with the sending operations 420A/420B of the sendinginterface 310, a substantial saved latency time T_(SL) is advantageouslyrealized over the FIG. 2 sequential operations. The cumulative latencytime saved over a plurality (e.g., thousands or millions) oftransactions is substantial, leading to a transaction forwardingarrangement which is very advantageous in terms of time savings at thecost of inconsequential further complexity of the queue/pointerarrangement and receiving interface. Such substantial time savings isvery favorable in this trend toward ever increasing computing speeds,and renders the transaction arrangement of the present invention verycompetitive within the marketplace.

[0044] An example implementation of the present invention will bebriefly described using the FIGS. 6, 7 example computing system,although practice of the invention is not limited thereto, i.e., theinvention may be able to be practiced with other types or arrangementsof computing systems. Turning now to FIG. 6, such FIG. 6 illustrates acollection of chips (e.g., including a chipset) and components whichimplement a mid-to-high end server platform. Shown are a plurality ofprocessors, a plurality of caches, a System Address Chip SAC and aSystem Data Chip SDC all arranged with respect to a front side bus FSBor processor BUS, and further shown is a Main Memory subsystem arrangedbetween, and accessed by, the SAC/SDC pair of integrated circuit (IC)chips.

[0045] The System Address Component SAC is one central component of achipset, and connects to the address and control sections of the frontside bus FSB, and is responsible for translating and directing FSBaccesses to an appropriate F16 bus or memory. It also acts as a routingagent for inbound traffic, directing traffic to a peer F16 bus, memoryor the FSB. The System Data Component SDC connects not only to the datasignals on the FSB, but also to the memory subsystem and the SAC (e.g.,via private bus PD and Control lines). The data for all transfers passesthrough the SDC, whether from the FSB to memory, from F16 to memory orpeer to peer F16. The connection between the SAC and SDC allows forconcurrent data transfers to the FSB and to the F16 buses. Thismaximizes the available bandwidth to each system agent.

[0046] Within the Main Memory subsystem, a Memory Address Component MACon memory cards receives signals on memory address MA lines, andtranslates memory cycles issued by the SAC into a protocol required bymemory chips (e.g., dynamic random access memories DRAM'S). There can bemultiple MAC's per memory card. The Memory Data Component MDC on thememory cards acts as a routing agent between the SDC and data pins ofthe memory array, i.e., with respect to data signals provided on memorydata MD lines. The MDC multiplexes data going into the SDC to select aproper data path for data coming from the memory array, and provides adistribution network for data being delivered to the memory. There maybe multiple MDCs per memory card.

[0047] Turning now to additional example components attached to the SACvia ones of a plurality of busses F16, a Peripheral ComputerInterconnect PCI eXpansion Bridge (PXB) may provide a bus protocolbridging function between the F16 bus and a PCI bus. A single PXB mayconnect to one F16 bus and may create multiple busses, e.g., two 33 Mhz,32 bit PCI buses. A strapping option may allow for the PXB to optionallysupport a single 64 bit PCI bus, and there may multiple PXBs within thesystem, e.g., from 1 to 4 PXBs. Additional components (not of interestto the understanding of the present disclosure) may be arranged inassociation with the PCI bus, e.g., a BIOS FLASH EPROM, PCI Device, aninterface bridge IFB acting as an input/output I/O bridge, IntegratedDevice Electronics hard-disk-drive IDE HDD, IDE CD-ROM, universal serialbus USB, etc.

[0048] In moving to yet an additional branch connected to the SAC, aGraphics eXpansion Bridge GXB provides a bus protocol bridging functionbetween another F16 bus arrangement and an Accelerated Graphics PortAGP. The addition of the GXB to the FIG. 6 system allows such system toaddress a mid-to-high end workstation market segment by adding a highperformance, dedicated graphics port.

[0049] Although the present invention is not limited thereto, the GXBwill be used to describe further details with respect to the exampleembodiment of the present invention. As shown in FIG. 7, the GXB may bepartitioned into various units for implementation purposes, for example,the GXB component may consist of the following graphics G units:Graphics AGP Interface (GAI) Unit; Graphics PCI Interface (GPI) Unit;Graphics Transaction Queue (GTQ) Unit; Graphics Data Buffer (GDB) Unit;Graphics Re-Mapping Table (GRT), also known as Graphics AddressRe-mapping Table (GART); Graphics F16 Ring (GFR) Interface Unit;Graphics Configuration and Status (GCS) Unit; Graphics PerformanceMonitor/Event (GPE) Logic Unit; Graphics Test and Debug (GTD) Unit;Graphics Clock and Reset (GCK) Unit; and Graphics Pad Ring (GPD) Unit.As but one example, the FIG. 3 example arrangement may be implementedwithin the FIGS. 6, 7 system by having the AGP Interface GAI arrangementadapted to function as the FIG. 3 Sending Interface 310 having theTransaction Queues GTQ arrangement adapted to function as the FIG. 3queue/pointer arrangement 320, and finally having the F16-R InterfaceGFR arrangement adapted to function as the FIG. 3 Receiving Interface380. Further, the GART may provide the operations of the TLB. Practiceof the present invention is not limited thereto, e.g., embodiments ofthe present invention could easily be practiced within any otherbridging component of FIG. 6, e.g., the PXB bridge, IFB bridge, SAC,etc.

[0050] Although example embodiments of the present invention weredescribed using an example system block diagram in an example serverenvironment, practice of the invention is not limited thereto, i.e., theinvention may be able to be practiced with other types of systems, andin other types of environments (e.g., personal computer (PC)).

[0051] As a conclusionary statement, reference in the specification to“one embodiment”, “an embodiment”, “example embodiment”, etc., meansthat a particular feature, structure, or characteristic described inconnection with the embodiment is included in at least one embodiment ofthe invention. The appearances of such phrases in various places in thespecification are not necessarily all referring to the same embodiment.Further, when a particular feature, structure, or characteristic isdescribed in connection with any embodiment, it is submitted that it iswithin the purview of one skilled in the art to effect such feature,structure, or characteristic in connection with other ones of theembodiments.

[0052] This concludes the description of the example embodiments.Although the present invention has been described with reference to anumber of illustrative embodiments thereof, it should be understood thatnumerous other modifications and embodiments can be devised by thoseskilled in the art that will fall within the spirit and scope of theprinciples of this invention. More particularly, reasonable variationsand modifications are possible in the component parts and/orarrangements of the subject combination arrangement within the scope ofthe foregoing disclosure, the drawings and the appended claims withoutdeparting from the spirit of the invention. In addition to variationsand modifications in the component parts and/or arrangements,alternative uses will also be apparent to those skilled in the art.

What is claimed is:
 1. A queue/pointer arrangement to queue at leastfirst execution information portions and second execution informationportions for transactions, said arrangement comprising: at least a firstqueue and second queue adapted to store said at least said firstexecution information portions and said second execution informationportions, respectively, said at least said first queue and said secondqueue having a first pointer arrangement and a second pointerarrangement, respectively, wherein said at least said first queue andsaid second queue operate independently of one another.
 2. Aqueue/pointer arrangement as claimed in claim 1, further comprising: asending interface adapted to transmit ones of said at least said firstexecution information portions and corresponding ones of said secondexecution information portions to said at least said first queue andsaid second queue, respectively, in at least one of differing times anddiffering transmissions.
 3. A queue/pointer arrangement as claimed inclaim 2, wherein said sending interface is adapted to transmit ones ofsaid at least said first execution information portions when informationthereof is complete, and to transmit corresponding ones of said secondexecution information portions when information thereof is complete,with each first execution information portion and a corresponding secondexecution information portion capable of being completed at mutuallydiffering times.
 4. A queue/pointer arrangement as claimed in claim 3,wherein ones of said at least said first execution information portionsand corresponding ones of said second execution information portionswith respect to said at least said first queue and said second queue,respectively, are at least address and full-line execution portions forones of said transactions.
 5. A queue/pointer arrangement as claimed inclaim 4, wherein one of said first queue and said second queue adaptedto receive said address portions, is adapted to begin performing anaddress translation operation on a received address portion irrespectiveof a completion of a corresponding full-line execution portion.
 6. Aqueue/pointer arrangement as claimed in claim 1, further comprising: areceiving interface adapted to receive ones of said at least said firstexecution information portions and corresponding ones of said secondexecution information portions from said at least said first queue andsaid second queue, respectively, in at least one of simultaneously,differing times and differing transmissions.
 7. A queue/pointerarrangement as claimed in claim 1, wherein at least one of said firstpointer arrangement and said second pointer arrangement is used toindicate ready ones of execution information portions queued within saidfirst queue and said second queue, respectively.
 8. A queue/pointerarrangement to queue at least first execution information portions andsecond execution information portions for transactions, said arrangementcomprising: at least a first queue means and second queue means forstoring said at least said first execution information portions and saidsecond execution information portions, respectively, said at least saidfirst queue means and said second queue means having a first pointermeans and a second pointer means, respectively, for pointing out readyones of said first execution information portions and said secondexecution information portions in said first queue means and said secondqueue means, wherein said at least said first queue means and saidsecond queue means operate independently of one another.
 9. Aqueue/pointer arrangement as claimed in claim 8, further comprising: asending interface adapted to transmit ones of said at least said firstexecution information portions and corresponding ones of said secondexecution information portions to said at least said first queue meansand said second queue means, respectively, in at least one of differingtimes and differing transmissions.
 10. A queue/pointer arrangement asclaimed in claim 9, wherein said sending interface is adapted totransmit ones of said at least said first execution information portionswhen information thereof is complete, and to transmit corresponding onesof said second execution information portions when information thereofis complete, with each first execution information portion and acorresponding second execution information portion capable of beingcompleted at mutually differing times.
 11. A queue/pointer arrangementas claimed in claim 10, wherein ones of said at least said firstexecution information portions and corresponding ones of said secondexecution information portions with respect to said at least said firstqueue means and said second queue means, respectively, are at leastaddress and full-line execution portions for ones of said transactions.12. A queue/pointer arrangement as claimed in claim 11, wherein one ofsaid first queue means and said second queue means for receiving saidaddress portions, is for immediately beginning performing an addresstranslation operation on a received address portion irrespective of acompletion of a corresponding full-line execution portion.
 13. Aqueue/pointer arrangement as claimed in claim 8, further comprising: areceiving interface adapted to receive ones of said at least said firstexecution information portions and corresponding ones of said secondexecution information portions from said at least said first queue meansand said second queue means, respectively, in at least one ofsimultaneously, differing times and differing transmissions.
 14. Aqueue/pointer arrangement as claimed in claim 8, wherein at least one ofsaid first pointer means and said second pointer means is for indicatingready ones of execution information portions queued within said firstqueue means and said second queue means, respectively.
 15. A systemcomprising: a queue/pointer arrangement to queue at least firstexecution information portions and second execution information portionsfor transactions, said arrangement comprising: at least a first queueand second queue adapted to store said at least said first executioninformation portions and said second execution information portions,respectively, said at least said first queue and said second queuehaving a first pointer arrangement and a second pointer arrangement,respectively, wherein said at least said first queue and said secondqueue operate independently of one another.
 16. A system as claimed inclaim 15, further comprising: a sending interface adapted to transmitones of said at least said first execution information portions andcorresponding ones of said second execution information portions to saidat least said first queue and said second queue, respectively, in atleast one of differing times and differing transmissions.
 17. A systemas claimed in claim 16, wherein said sending interface is adapted totransmit ones of said at least said first execution information portionswhen information thereof is complete, and to transmit corresponding onesof said second execution information portions when information thereofis complete, with each first execution information portion and acorresponding second execution information portion capable of beingcompleted at mutually differing times.
 18. A system as claimed in claim17, wherein ones of said at least said first execution informationportions and corresponding ones of said second execution informationportions with respect to said at least said first queue and said secondqueue, respectively, are at least address and full-line executionportions for ones of said transactions.
 19. A system as claimed in claim18, wherein one of said first queue and said second queue adapted toreceive said address portions, is adapted to begin performing an addresstranslation operation on a received address portion irrespective of acompletion of a corresponding full-line execution portion.
 20. A systemas claimed in claim 15, further comprising: a receiving interfaceadapted to receive ones of said at least said first executioninformation portions and corresponding ones of said second executioninformation portions from said at least said first queue and said secondqueue, respectively, in at least one of simultaneously, differing timesand differing transmissions.
 21. A system as claimed in claim 15,wherein at least one of said first pointer arrangement and said secondpointer arrangement is used to indicate ready ones of executioninformation portions queued within said first queue and said secondqueue, respectively.
 22. A queue/pointer method to queue at least firstexecution information portions and second execution information portionsfor transactions, said method comprising: providing at least a firstqueue and second queue adapted to store said at least said firstexecution information portions and said second execution informationportions, respectively, said at least said first queue and said secondqueue having a first pointer arrangement and a second pointerarrangement, respectively, wherein said at least said first queue andsaid second queue operate independently of one another providing asending interface adapted to transmit ones of said at least said firstexecution information portions and corresponding ones of said secondexecution information portions to said at least said first queue andsaid second queue, respectively, in at least one of differing times anddiffering transmissions, wherein said sending interface transmits onesof said at least said first execution information portions wheninformation thereof is complete, and transmits corresponding ones ofsaid second execution information portions when information thereof iscomplete, with each first execution information portion and acorresponding second execution information portion capable of beingcompleted at mutually differing times.